The ideas behind reconfigurable computing are based on the concept of a processing unit coupled to an array of "reconfigurable" hardware. The reconfigurable hardware is tailored to perform a specific task. Once the task is executed, the processor adjusts the hardware to the next task, etc.
This concept allows the reconfigurable hardware to switch from one task (for instance, image processing) to the next processing task in a matter of microseconds or less. On the other hand, it also allows the reconfigurable hardware to perform completely different tasks in the future.
Fully programmable cores - like general-purpose processors (GPP) - can compute virtually any algorithm. Unfortunately, the overhead caused by this flexibility makes them very inefficient. On the other hand, application-specific cores (ASIC), are very efficient but offer no flexibility as they are not programmable by definition.
Our Recore reconfigurable core technology offers the best of both worlds by maximizing flexibility and efficiency.
The ambition of so-called domain-specific reconfigurable cores is that the hardware adapts to the algorithm, instead of adapting the algorithm to the hardware. Careful configuration of the hardware to the desired performance programmed into the algorithm maximizes efficient utilization of the resources.