Reconfigurable cores in Systems on Chip

It is possible to rapidly develop complete Systems-on-Chip (SoC) by reusing and reconfiguring hardware and software components, including Recore’s Montium® and Xentium® cores. Montium and Xentium technology can be used in various topologies:

  1. in a SoC to function as a reconfigurable DSP accelerator;
  2. in a multi-core or in a many-core processor to benefit from excellent DSP computational power and superior scalability.

Co-processor model

Co-processor model

One or more Montium or Xentium cores can be used as a reconfigurable DSP hardware accelerator in combination with a general purpose processor (GPP). The Montium or Xentium cores are reprogrammed for the dedicated DSP functionality.

Communication in a small SoC is usually established via an on-chip bus (e.g. AMBA) with a simple programming model.

Multi-core/many-core model

Multi-core model

Several Montium or Xentium cores can be combined together in a more autonomous way, where data is streamed through the SoC. The autonomous DSP kernels are mapped on the individual, domain-specific cores in the SoC.

The communication infrastructure of these multi-core SoCs is generally based on Network-on-Chip (NoC) technology. The advantage of a NoC is that it is very scalable: communication capacity increases with the size of the system.

The processing tiles are connected within the NoC by network interfaces and bridges. The heterogeneous system comprises a variety of hardware modules. A standard bus connects the multi-core system to other components such as embedded processors, high-performance peripherals, DMA controllers, on-chip memory and interfaces, or a GPP subsystem.

Using Recore’s Montium and Xentium cores in a multi-core topology provides a flexible environment which is scalable for many kinds of complex DSP applications, from digital broadcasting and multimedia handsets to high-end specialist applications.