Publications

Several papers about Recore's technology have been published in international journals and conference proceedings. Below you will find a selection to provide you with background information on reconfigurable computing, its challenges and its uses.

Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP

International Journal of Reconfigurable Computing: Volume 2009, article 678045

Coarse-grained reconfigurable architectures like the Montium® TP have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and flexibility of the implementation.

Tailored SoC building using reconfigurable IP blocks

IP Conference Paper, December 2008.

Increasing complexity, fast-changing standards and shorter time to market call for composing systems out of standard IP components. An example shows the construction of a System-on-Chip (SoC) based on standard IP components for a Digital Audio Broadcasting consumer application.

Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

FPL Conference Paper, August 2007

This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium processor. This shows that the IDCT can be mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.

Coarse-Grained Reconfigurable Computing for Power Aware Applications

ERSA Conference Paper, June 2006

Reconfigurable architectures find the middle ground between flexibility and efficiency by limiting their flexibility to a particular algorithm domain. A domain specific reconfigurable architecture is both efficient and flexible. Recore Systems provides semiconductor IP solutions for programmable systems-on-chip. The coarse-grained reconfigurable technology of Recore promises to solve the flexibility, performance, power consumption and cost requirements of semiconductor businesses.