Glossary

ASIC

application-specific integrated circuits

Configware

In order to change the functional behavior of a reconfigurable DSP accelerator, the accelerator is (re)configured by Configware. Configware comprises source code and binaries that define the DSP functions implemented on a reconfigurable DSP accelerator core. Once the configuration is set, no further programming of the reconfigurable accelerator is required and it will act as an ASIC implementation. The accelerator implementation can be set via the ConfigWare API.

GPP

general-purpose processor

Locality of reference

Small data memories closely connected to the data processing units avoid inefficient data transfers. Locality of reference principles in SoC designs guarantee that data is stored as close as possible to the data processing unit. The lack of data communication in a SoC results in energy efficiency.

Montium^®

The Montium is a dynamically reconfigurable IP core for computation-intensive DSP algorithms. The Montium processor contains parallel data processing units as well as small data memories to store the processed data locally. The Montium combines the efficiency of an ASIC with the programmability of a DSP. ASIC-like performance and energy-efficiency is obtained by dynamically configuring the Montium with the functionality required by the algorithm at hand. The Montium can be reconfigured virtually instantly, as the size of the configuration binaries is very small. This enables efficient reuse of hardware at run-time, and silicon costs remain low due to the very small silicon footprint.

The Montium is typically integrated as a reconfigurable DSP accelerator next to a general purpose processor in a SoC. The reconfigurable DSP accelerator is configured with the DSP functionality required using Recore's Configware.

Reconfigurable computing

In a reconfigurable computer, the standard processor controls one or more pieces of reconfigurable hardware. The reconfigurable hardware is tailored to perform a specific task as quickly as dedicated hardware. Once the task is done, the processor adjusts the hardware to the next task, etc.

Xentium^®

The Xentium processor consists of the Xentium core, a network interface (NI), and data memory. The Xentium core is a fixed point VLIW-DSP core designed for high-performance embedded signal processing. High performance and energy efficiency are achieved by optimizing parallel operation at instruction level. Parallel data memory banks are included in the Xentium processor so that data is stored close to the data processing units (i.e. locality of reference).