Based on Recore Systems’ multicore Digital Signal Processor (DSP) subsystem IP, the “Massively Parallel Processor Breadboarding (MPPB) Study” (ESA Contract No. 21986) developed a scalable heterogeneous multicore System-on-Chip (SoC) architecture and a payload unit prototype for future sensor data processing in space applications.
The payload unit prototype implements an instantiation of the SoC architecture on a Xilinx Virtex-5LX330T FPGA.
All functional interfaces are available on the front-panel of the MPPB unit, such as LCD, SpaceWire, ADC input interface, DAC output interface, debug and program interface, and general purpose IO.
The developed multicore DSP SoC architecture combines the benefits of heterogeneity and integration in a scalable and energy-efficient architecture.
The architecture comprises a System-on-Chip integrating on one chip multiple processing cores with SpaceWire (including RMAP protocol support), CCSDS timers, ADC/DAC interfaces, and on-chip as well as off-chip memories. In general, data interfaces are connected directly to the NoC of the DSP subsystem and control interfaces and peripherals are placed on the bus of the GPP subsystem.
The architecture includes Recore’s scalable DSP subsystem and a General-Purpose Processor (GPP) system. The DSP subsystem is a customization of Recore’s multicore DSP subsystem IP based on Xentium® DSP processors in a Network-on-Chip (NoC). The GPP subsystem is based on Cobham Gaisler’s LEON2 microprocessor with a conventional bus subsystem.
The payload unit prototype features include:
Xentium DSP processors
Xentium performance counters
Clock and Reset Manager (CRM)
A firmware upgrade of the MPPB unit is available for evaluation of new candidate IP features for the Scalable Sensor Data Processor (SSDP) IC under development. The new firmware can be used with the existing HW configuration. The upgrade improves programmability with amongst others Xentium multicore debugging, Xentium performance counters, and additional DMA features.