Fault-tolerant, adaptive Network-on-Chip IP

Network-on-Chip interconnect technology for scalable multi- and many-core System-on-Chip architectures

  • Scalable, deterministic, predictable, deadlock-free
  • Fault tolerant by design
  • AMBA 2 compatible


The NoC IP building blocks allow for easily developing heterogeneous multi-core processor architectures.


Target applications

  • Heterogeneous multi-core processor architectures
    • Reliable data payload processing in space
    • Any application that requires highly reliable component interconnects

General description

The fault-tolerant Network-on-Chip IP is specifically designed to quickly and reliably route data from core to core in multi- and many-core System-on-Chips (SoCs) that are used in extreme conditions.

The NoC IP implements packet-switched NoC technology using dimensional XY-routing and wormhole switching in a two-dimensional mesh network.

The NoC IP implements fault-tolerance techniques and combines the determinism of XY-routing with explicitly programmable adaptiveness to provide a controlled manner for routing traffic around congested or faulty network elements, while preserving determinism and deadlock freedom.

Easy to use NoC IP package

The NoC IP is technology agnostic, and can be synthesized for FPGA and ASIC targets.

The detault IP package comprises a complete IP package with VHDL sources, testbenches for the NoC Router and AMBA Network Interface, scripting, and documentation. It is further complemented by functional SystemC models, traffic monitoring configurations and scripting for throughput performance analysis.

The IP package contains:

  • Configurable VHDL of NoC Router, including standalone testbench;
  • Configurable VHDL of AMBA NI, including stand-alone testbench;
  • SystemC model for early software development.

IP blocks

The main IP building blocks of a scalable Network-on-Chip are the Router IP and the AMBA Network Interface IP.

  • Router IP: Using the North, East, South and West ports of the 5-port Router IP block it is straight forward to instantiate a 2D-mesh network.
  • AMBA NI IP: The AMBA Network Interface provides AHB master and AHB slave interfacing for connecting IP components to the Local port of the 5-port NoC Routers

Using the AMBA NI one can easily connect AMBA AHB-based IP blocks in a memory-mapped NoC architecture.

Contact us for customizing Network Interfaces for e.g. streaming ADC, DAC, SpaceWire, SpaceFibre, etc.

Contact us for building scalable Network-on-Chip architectures; getting the best out of the NoC using Recore's NoC-DMA controller. The NoC-DMA controller efficiently uses the NoC Indirect Transaction protocol features without using processing resources of the system's host processor. 

Performance - Area/Speed

The NoC IP runs at 180 MHz, 500 MHz and 1 GHz clock frequency in DARE180, C65SPACE and FDSOI28 ASIC technology, respectively.

Customer Case

The NoC IP has been validated in a 3x3 NoC-mesh platform with multiple LEON3FT processing elements in FPGA. The 3x3 NoC-mesh multi-core platform runs at 40 MHz clock frequency in a Virtex-4 device. This FPGA-based platform has been validated while running parallelized JPEG compression software, spreading work over several processing elements.



  • 32-bit packet-switched 2D-mesh network
  • XY-routing, deadlock-free
  • 5-port Routers featuring 4 prioritized services (using virtual channels)
  • Quality of Service provided by prioritized services
  • 32-bit data transfer per NoC link (per single direction)

Fault-resilient, reliable and adaptive

  • Adaptive XY-routing provides data rerouting in the NoC in case of congestion or permanent connection errors
  • Flit-level flow control for more robust error signaling
  • Enable the insertion of EDAC for transient error protection on data links to increase robustness of data

Network-on-Chip protocol packets

  • Single read/write transactions
  • Block read/write transactions
  • Interrupt packet signaling
  • Support for Indirect transactions (i.e. slave-to-slave operations using DMA controller)


Network-on-Chip Interfaces

Network Interfaces connect IP components to the Local port of the NoC Router, such as

  • SpaceWire interfaces,
  • DAC converters,
  • Recore‚Äôs Xentium DSP,
  • AMBA 2 compatible building blocks, e.g. GRLIB IP

AMBA Network Interface - AMBA NI

  • Transparent interfacing between NoC and AMBA domain

    • Access to memory-mapped I/O on NoC

    • 32-bit AHB-lite master/slave ports

  • Interrupt signaling interface for NoC interrupt packets

  • Interrupt signaling and forwarding of devices to NoC

Clock and Reset

  • Single NoC clock domain

  • Synchronous reset input


Ready to try it?

  • Xentium and NoC IP are available via Recore Systems. For more details contact us.
  • With the Xentium simulator, you can test, time and trace Xentium executables on your PC. Contact us for a license.
  • To test your target applications on the functional payload unit prototype we offer evaluation opportunities. For more details contact us.
  • Packaged and functionally tested prototype SSDP ASICs, suitable for prototype / EM systems, instruments, and data processing units, are expected to be available soon. For more details contact us.