Montium FFT/IFFT core
Recore Systems’ Montium® FFT/IFFT IP core is a decimation-in-time (DIT) radix-2 implementation of the Cooley-Tukey FFT/IFFT algorithm implemented in MontiumC on a Montium hardware IP core. The Montium FFT/IFFT IP core requires the minimum number of clock cycles in order to compute FFTs on real or complex data up to lengths of 8192 points. As an example, a typical 1024-point FFT/IFFT requires just 5140 cycles, or 51.4 µs when clocked at 100 MHz.
Montium butterfly mapping
Using a complex multiplier operation in combination with the flexibility of the Montium datapath, it is possible to implement an FFT/IFFT butterfly in a single clock cycle using only 4 arithmetic logic units (ALUs). This demonstrates the efficiency of the hardware architecture.
