Recore Systems releases a many-core processor subsystem IP-on-FPGA

3-03-2014

Recore Systems today releases a many-core processor subsystem IP connecting Recore Xentium DSP cores, a General Purpose Processor, and other IP blocks in a heterogeneous many-core processor architecture via a hybrid Network-on-Chip/AMBA bus interconnect. To facilitate programming, the many-core processor subsystem IP comes with a Software Development Environment, a many-core functional simulator, and dedicated libraries.

The Recore many-core processor subsystem IP-on-FPGA merges two to four Xentium VLIW DSP processor cores and up to five other IP cores, connected via a proprietary Network-on-Chip (NoC).  The hybrid Network-on-Chip/AMBA bus interconnect combines the best of both worlds: it promotes efficient data transfer via a Network-on-Chip (NoC) in the DSP subsystem, yet facilitates easy compatibility in a GPP subsystem with off-the-shelf general purpose processors (GPP), traditional IP blocks, and an AMBA bus. The Recore many-core processor subsystem IP-on-FPGA is instantiated on a Xilinx Virtex-6 FPGA.

For developing DSP applications and generating target code, the Recore many-core processor sub-system IP comes with the Xentium Studio Software Development Environment (SDE), an Eclipse IDE plug-in which can easily be integrated with any General Purpose Processors supporting the Eclipse IDE. The SDE can be supplemented with a functional many-core simulator for simulating applications on the Recore many-core processor subsystem IP. The functional simulator unites a GPP and up to four Xentium DSP cores in a preconfigured many-core simulation environment of choice.

 

Read all details on the many-core processor subsystem IP-on-FPGA here....