Processors for Space

16-09-2013

The Italian website ElettronicaNews explained Recore's fault-tolerant DSP FPGA  prototype solution for space applications (MPPB) in its article on 'Processors for Space'.

A few excerpts from the article:

Processors for space

The space industries' increasing demand for more computational power and data transmission has led to the development of processors with unparalleled performance.
Editor: Mariano Severi - Electronics Section

For space applications - just like in all other application fields - processors are an essential component of digital architectures, and are used both for control purposes and for data processing. When searching the net, it is not difficult to find a (non-exhaustive) overview  of some of the main CPUs used in the public sector and its reference missions over the years. [...]

MPPB

An alternative approach to those presented above [see article] in the race for higher performance DSPs for space applications is that of massively parallel architectures. An example of this is the project MPPB (Massively Parallel Processor Breadboarding) conducted by Recore Systems on behalf of ESA. A FPGA prototype of the system was presented last August at the 'DSP Day' event held in ESA's headquarters in the Netherlands.

In the course of this year, we expect results of the first implementation of major functional MPPB modules in radiation-hard ASIC technology (through Imec DARE 180 nm process libraries). MPPB is based on a NoC (Network On Chip) scalable architecture that interconnects Xentium DSP cores  (developed by the same Recore Systems) operating in parallel.

Xentium is a VLIW core programmed directly in the C language and supports scalar operations in 32/40-bit, or 2 16-bit vector elements, with up to 10 slots for parallel execution; it natively supports fixed-point data format with the ability to emulate instructions on floating-point operands. MPPB is controlled by a Leon-2 CPU, which also manages the instructions to individual DSP cores. MPPB integrates a 256 Kbyte on-chip memory and an external SDRAM memory controller, DMA controller and embedded 2-port SpaceWire communication (including one with support for RMAP) as well as classical devices such as GPIO, UART and LCD.

The MPPB architecture also implements mechanisms of self-repairing, implemented as the possibility of automatic detection of possible faulty DSP cores. Faulty DSP cores are isolated from the network and the core's tasks are rerouted to alternative DSP cores, eventually reducing performance while always ensuring the correct execution of all task.

Translation based on Google Translate