Concluded research projects


BENEFIC (Best ENergy EFficiency solutions for heterogeneous multI-core Communicating systems) is a cross-industry research & development project consisting of 25 organizations including industrial, SME and university partners from France, the Netherlands, and Portugal.

The BENEFIC project is a CATRENE funded project.

Read more on BENEFIC on the project website....


Sensation gave embedded system designers tools to develop complete products that are energy-wise self-supporting. The Sensation tools we developed allow programmers to easily develop Energy Centric Systems that reconfigure themselves in view of harvested and consumed energy, changing tasks, resources, and errors.

Read more on SENSATION on the project website....


The Sensor Technology Applied in Reconfigurable Systems for Sustainable Security project, an initiative of the Dutch government, developed the technology to build reconfigurable sensor networks which can quickly adapt to the changing nature of security threats.


ALMA (Greek for ‘leap’) is an acronym for ALgorithm parallelization for Multicore Architectures.  ALMA intends showed how various embedded reconfigurable multi-cores from Recore Systems and Karlsruhe Institute of Technology can be efficiently programmed using the same tool-chain and the same application code.

Read more on ALMA on the project website...


To counter the increasing fault-rates expected for the next technology generations, DeSyRe develops new design techniques for future SoCs to improve reliability while at the same time reducing power / performance overheads associated with fault-tolerance.

Read more on DeSyRe on the project website...


The Tracking, tracing, Sensoring Platform aims to research and develop a new generation of electronic Radio Frequency Identification (RFID) technology for commercial use.

Read more on TSP on the project website...



COmmunication-centric heterogeneous Multi-Core ArchitectureS was a CATRENE project aimed at breakthrough low-power design solutions for (data) communication-centric heterogeneous multi-core architectures targeting 45 nm and 32 nm CMOS technologies. During the project, we designed a multi-core architecture and validated its use with a software-defined radio application.


3D-TSV Integration for Multimedia and Mobile Applications finished in December 2012. It was a CATRENE project with the aim to enable the design and implementation of heterogeneous SoCs (system-on-chip), using the emerging 3D TSV (through-silicon via) technology. 


CRISP (Cutting edge Reconfigurable ICs for Stream Processing) was successfully completed in mid 2011 with a General Stream Processor IC. CRISP demonstrated that it is possible to use one single highly scalable reconfigurable system for a wide range of streaming applications. Two applications at both ends of the complexity spectrum validated the approach: both satellite navigation and digital beamforming could be successfully implemented over 5 respectively 39 Xentium DSP cores in the General Stream Processor. 

Recore contributed its Xentium IP core and design knowlegde for scalable many-core architectures to the project.

Crisp was a FP 7 project.

4S project

4S project

The Smart Chips for Smart Surroundings (4S) project finished in December 2007. Its aim was to create flexible and reconfigurable building blocks for new consumer devices and applications in for instance digital information broadcasting, ambient intelligence devices, and 3G/4G multimedia terminals.

The project provided proof of concept of power-efficient reconfigurable computing, and delivered 2 concept chips: a digital baseband chip and an analogue frontend chip. Recore contributed its Montium® IP and knowledge of reconfigurable SoCs to the project's digital baseband chip.

An ARM 9 General Purpose Processof and the project's digital baseband chip were compared for energy efficiency and speed. Including memory accesss, the Montium-based SoC reduced energy use when running non-power-of-two FFTs by a factor of 33 compared to the General Purpose Processor (excluding memory access). In a comparison of processing time, relative speed increased by a factor of 40.

4S was an EU Framework 6 project.


SCALOPES succesfully completed in 2011 and received the ARTEMIS Recognition Certificate in the same year.  "Given the breadth of the project and its short duration, the results achieved have been impressive," to quote the certificate.

SCALOPES (SCAlable LOw Power Embedded PlatformS) focused on cross-domain technology and tool development for multi-core architectures. The SCALOPES consortium comprised many industrial partners and research institutions from all over Europe.

Recore contributed to code generation technologies for reconfigurable, multi-core SoCs with - to be specific about Recore technology - Xentium IP inside.

SCALOPES was an ARTEMIS project.